1. Field of the Invention
The present invention relates to an integrated circuit and, more particularly to an integrated circuit for performing a burn-in test at the wafer level of semiconductor production and a testing method using the same.
2. Description of the Related Art
Integrated circuits including DRAM and SRAM memory cells often fail due to defects in the manufacturing process. To screen such failures, a burn-in test is performed on the integrated circuits. In the burn-in test, a write operation is repeatedly performed under a high voltage and at a high temperature. The burn-in test is performed after the integrated circuit is packaged. In other words, circuit chips are electrically tested in a wafer state during manufacturing. The chips that pass the wafer test are packaged and the burn-in tested. The burn-in test is often called package burn-in (PBI).
The burn-in time increases as the integration level of the circuit increases. Additionally, integrated circuits are made with a wider variety of functions and pins, the socket density of a burn-in board is reduced. Accordingly, productivity deteriorates. Also, package yield worsens since initial failure is not appropriately detected at the wafer level.
Various water burn-in level methods have been developed to address the above-related problems. One such method is described in U.S. Pat. No. 5,294,776 to Kuruyama assigned to Kabushiki Kaisha Toshiba of Japan. There, all dies in a wafer are electronically stressed during burn-in by applying a higher than normal supply voltage Vcc and ground voltage Vss. In the Furuyama patent the stress applied is direct current (DC) voltage. This is because an alternating current voltage cannot be reliably sequentially and repeatedly applied to all of the memory cells.
It is an object of the present invention to provide an integrated circuit capable of being effectively burn-in tested by reliably sequentially and repeatedly applying an AC stress to all memory cells contained therein.
There is provided an integrated circuit including a plurality of memory cells arranged in rows and columns and having at least one test mode. The integrated circuit according to the present invention comprises an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory cell selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory cell.
Also provided is a semiconductor wafer including a plurality of dies arranged in columns and rows, each die includes a plurality of memory cells, a normal and at least one test mode, and a scribe lane positioned between adjacent dies. A test supply line for receiving an external test power supply in the test operation mode is positioned in the scribe lane. Each die comprises a switch for coupling the test supply line to the normal supply line in the test mode and uncoupling the test supply line from the normal supply line in the normal mode, responsive to a control signal. The voltage level of the data provided to the memory cell is controlled by the voltage level of the normal supply line.
Also, provided is a method for testing a plurality of integrated circuit dies arranged in rows and columns on a wafer, each die including a plurality of memory cells. The method comprises the steps of counting a clock signal, generating an address signal for a selected memory cell responsive to the counted clock signal, generating a data signal responsive to the clock signal, and providing the data signal to the selected memory cell.
The integrated circuit and the semiconductor wafer of the present invention, allow effective wafer burn-in testing by sequentially and repeatedly applying the AC stress to a plurality of memory cells while minimizing current consumption.